Semiconductor packages having increased input/output capacity and related methods

ABSTRACT

A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/026,991, filed on Feb. 14, 2011, which claims priority to TaiwanPatent Application No. 99131048, filed on Sep. 14, 2010. The subjectmatter of the priority applications is incorporated by reference hereinin its entirety.

TECHNICAL FIELD

The present disclosure relates to semiconductors and more particularlyto semiconductor assembly and packaging.

BACKGROUND

Flat No leads packages, such as Quad Flat No leads (QFN), operationallycouple integrated circuits to printed circuit boards. The QFN packagestructure typically includes a semiconductor chip, a die pad upon whichthe chip is located, an array of leads, and a package body. A pluralityof bonding wires electrically connects the chip to upper surfaces of theleads. Exposed lower surfaces of the leads are used as the externalcontacts of the QFN package structure. The leads are generally arrangedin a perimeter array circumscribing the chip. An area beneath the chipmay include leads, but they are typically not used for input/output(I/O). It is desirable to increase the I/O capacity of QFNs.

SUMMARY

One embodiment of the present semiconductor packages comprises asemiconductor chip, a plurality of first leads, and a plurality ofsecond leads. Each of the second leads is disposed at least partiallyunder the chip, and has an upper sloped portion and a lower slopedportion meeting at a peak. The semiconductor package further comprises aplurality of bonding pads extending outside a periphery of the chip, anda plurality of connecting segments connecting each bonding pad to arespective one of the second leads. A filling material occupies spacesbetween the chip and the upper sloped portions of the second leads.

Another embodiment of the present semiconductor packages comprises asemiconductor chip, a plurality of first leads, and a plurality ofsecond leads. Each of the second leads is disposed at least partiallyunder the chip. The semiconductor package further comprises a pluralityof bonding pads extending outside a periphery of the chip, and aplurality of connecting segments connecting each bonding pad to arespective one of the second leads. Upper surfaces of the first leads,the second leads, the bonding pads and the connecting segments arecoplanar.

One embodiment of the present semiconductor packaging processescomprises forming a patterned first metal plating layer on a top surfaceof a conductive substrate. The first metal plating layer comprises aplurality of first lead metal patterns located outside of a chip bondingregion of the substrate, a plurality of bonding pad metal patternslocated outside of the chip bonding region, a plurality of second leadmetal patterns located within the chip bonding region, and a pluralityof connecting segment metal patterns extending between the second leadmetal patterns and the bonding pad metal patterns. The semiconductorpackaging process further comprises forming a patterned second metalplating layer on an undersurface of the conductive substrate. Theprocess further comprises performing a half etching process on the topsurface of the conductive substrate to form recessed areas in the topsurface, including recessed areas in the chip bonding region, therecessed areas including upper sloped portions. The process furthercomprises inserting a filling material into the recessed areas in thechip bonding region, such that the filling material occupies spacesbetween the upper sloped portions of the recessed areas. The processfurther comprises bonding a semiconductor chip in the chip bondingregion of the conductive substrate, wherein the chip is located abovethe filling material and the second lead metal patterns. The processfurther comprises wire bonding the semiconductor chip to the bonding padmetal patterns and to the first lead metal patterns through a pluralityof bonding wires. The process further comprises etching the undersurfaceof the conductive substrate to form a plurality of first leads locatedoutside of the chip bonding region, a plurality of bonding pads locatedoutside of the chip bonding region, a plurality of second leads locatedwithin the chip bonding region, and a plurality of connecting segmentsextending between the second leads and the bonding pads.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional view of a semiconductor package structureaccording to one of the present embodiments;

FIG. 1B is a top plan view of the semiconductor package structure ofFIG. 1A;

FIG. 1C is a detail view of the portion of FIG. 1A indicated by thecircle 1C-1C;

FIGS. 2A-2J are cross-sectional views of various steps in asemiconductor packaging process according to one of the presentembodiments;

FIGS. 3A-3I are cross-sectional views of various steps in asemiconductor packaging process according to another of the presentembodiments;

FIGS. 4A-4J are cross-sectional views of various steps in asemiconductor packaging process according to another of the presentembodiments; and

FIGS. 5A-5I are cross-sectional views of various steps in asemiconductor packaging process according to another of the presentembodiments.

Common reference numerals are used throughout the drawings and thedetailed description to indicate the same elements. The presentinvention will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

Referring to FIGS. 1A-1C one embodiment of the present a semiconductorpackage structures 200 is illustrated. The package 200 comprises a chipor die 210, a plurality of first leads 222 and second leads 224, aplurality of bonding pads 226, a plurality of connecting segments 228, aplurality of bonding wires 230, a filling material 240 and a moldingcompound 250 also referred to as a package body or an encapsulant. Forclarity, FIG. 1B omits the bonding wires 230 and the molding compound250 shown in FIG. 1A, and illustrates one example of routing for theconnecting segments 228, as discussed further below.

With reference to FIG. 1B, the second leads 224 are located under orpartially under the chip 210. The connecting segments 228 connect thebonding pads 226, which are disposed outside a perimeter of the chip210, to the second leads 224. In FIG. 1B, the connecting segments 228are shown with an angular offset routing. However, the routing may be astraight linear path as well as other angled paths between the bondingpads 226 and the second leads 224. In certain embodiments, the routingmay be a combination of straight linear path as well as angled paths.

With reference to FIG. 1C, each of the first leads 222 comprises anupper surface 222 a, a lower surface 222 b, an upper sloped portion 222c adjacent to the upper surface 222 a and a lower sloped portion 222 dadjacent to the lower surface 222 b. Each of the second leads 224comprises an upper surface 224 a, a lower surface 224 b, an upper slopedportion 224 c adjacent to the upper surface 224 a and a lower slopedportion 224 d adjacent to the lower surface 224 b. The sloped portionsof the leads 222 and 224 may be slightly concave due to themanufacturing etch process. The upper surfaces 222 a and 224 a aresubstantially coplanar and the lower surfaces 222 b and 224 b are alsosubstantially coplanar. For the first leads 222, a peak 222 e may beformed where each upper sloped portion 222 c meets its respective lowersloped portion 222 d. Likewise, for the second leads 224, a peak 224 emay be formed where each upper sloped portion 224 c meets its respectivelower sloped portion 224 d. The peaks 222 e, 224 e may fullycircumscribe their respective leads 222, 224. However, the peaks 224 eon the second leads 224 may not fully circumscribe the second leads 224due to the connecting segments 228.

With reference to FIG. 1A, the bonding wires 230 electrically connectthe chip 210 to the first leads 222 and the bonding pads 226. Asdiscussed above, the second leads 224 are located under the chip 210,the bonding pads 226 are configured outside a periphery of the chip 210,and the connecting segments 228 connect the bonding pads 226 and thesecond leads 224. The bonding wires 230 thus electrically connect thechip 210 to the second leads 224 under the chip 210 through the bondingpads 226 and the connecting segments 228 so that the second leads 224can be used for input/output (I/O).

With reference to FIGS. 1A and 1C, the molding compound 250substantially covers the upper sloped portions 222 c of the first leads222 and the upper sloped portions 224 c of some of the second leads 224.The lower sloped portions 222 d of the first leads 222 and at least someof the lower sloped portions 224 d of the second leads 224 protrude fromthe undersurface 250 a of the molding compound 250. The filling material240 is interposed between the chip 210 and the second leads 224,particularly the upper sloped surfaces 224 c of the second leads 224. Inthe illustrated embodiment, the molding compound 250 is formed about thechip 210, the bonding pads 226, the connecting segments 228, the bondingwires 230, the leads first leads 222 and a portion of the second leads224. In certain embodiments, the molding compound 250 may extend aroundthe peaks 222 e, 224 e of some or all of the leads 222, 224. In suchembodiments, the molding compound 250 provides a mechanical hold on theleads 222, 224, making it less likely that the leads 222, 224 willrelease from the molding compound 250. However, in other embodiments theundersurface 250 a of the molding compound 250 may be substantiallycoplanar with the peaks 222 e, 224 e.

The compositions of the filling material 240 and the molding compound250 may be the same or different from one another. Thus, in a process ofmaking the package 200, the filling material 240 may be formed in thepackage 200 in one step, and then the molding compound 250 is formed ina later step. Alternatively, the step of forming the filling material240 can be omitted and the molding compound 250 can fill the spacesbetween the chip 210 and the second leads 224 when the molding compound250 is formed. One advantage of forming the filling material 240 inadvance of the molding compound 250 is to form a flat region for placingthe chip 210 so that the stability of the chip 210 is enhanced. Inalternative embodiments, the thickness of the filling material 240 canbe changed according to prevailing requirements so that the elevation ofthe exposed surface of the filling material 240 is higher than, equalto, or lower than the upper surfaces 224 a of the second leads 224.

With reference to FIG. 1C, the illustrated embodiment includes anadhesion layer 270 disposed between the undersurface 210 a of the chip210 and the filling material 240. Advantageously, the filling material240 may prevent the optional adhesion layer 270 on the undersurface ofthe chip 210 from being exposed in later process steps. The fillingmaterial 240 may be, for example, and without limitation, a polymermaterial, a solder mask, a dry film material, or an epoxy resin madefrom a dispensing process. When epoxy resin is used as the fillingmaterial 240, the filling material 240 can perform the dual functions ofadhering and fixing the chip 210, allowing the adhesion layer 270 to beomitted.

With reference to FIG. 1A, in some embodiments a first metal platinglayer 262 may be provided on the upper surface 222 a of each of thefirst leads 222, the upper surface 224 a of each of the second leads224, the bonding pads 226 and the connecting segments 228. The uppersurfaces 222 a of the first leads 222 and the first metal plating layer262 thereon are enclosed within the molding compound 250. The uppersurfaces 224 a of the second leads 224 and the first metal plating layer262 thereon are enclosed within the filling material 240 and/or themolding compound 250. The first metal plating layer 262 may serve as anetching mask while the upper portions of the first leads 222 and thesecond leads 224 are formed. The first metal plating layer 262 may alsoenhance the bond between the bonding wires 230 and the first leads 222,and between the bonding wires 230 and the bonding pads 226. Morespecifically, the first leads 222 and/or the second leads 224 may be,for example, copper. The first metal plating layer 262 may be, forexample, gold, sliver, a nickel/gold stacked layer or anickel/palladium/gold stacked layer. The bonding wires 230 can beeffectively bonded to the surface of the first metal plating layer 262.Similarly, a second metal plating layer 264 may be disposed on the lowersurfaces 222 b of the first leads 222 and the lower surfaces 224 b ofthe second leads 224. The composition of the second metal plating layer264 may be similar to or different from the composition of the firstmetal plating layer 262. In the illustrated embodiment, the bonding pads226 and the connecting segments 228 are not covered by the second metalplating layer 264.

As illustrated in FIG. 1A, a die pad 290 may be optionally formed underthe chip 210. The a die pad 290 is electrically isolated from the firstleads 222 and the second leads 24. In this embodiment, the second leads224 occupy only a portion of the area under the chip 210, while the diepad 290 occupies the remaining space under the chip 210 and supports thechip 210. The die pad 290 may also serve as a heat sink to enhance heatdissipation from the chip 210.

FIGS. 2A-2J are cross-sectional views illustrating a semiconductorpackaging process according to one of the present embodiments. Referringto FIGS. 2A-2C, a first metal plating layer 262 and a second metalplating layer 264 are formed on a top surface 202 a and on anundersurface 202 b, respectively, of a conductive substrate 202. Withreference to FIG. 2A, the method for forming the first metal platinglayer 262 and the second metal plating layer 264 may comprise forming afirst patterned mask 282 on the top surface 202 a of the conductivesubstrate 202. The top surface 202 a of the conductive substrate 202 hasa chip bonding region 204. In the present embodiment, the firstpatterned mask 282 can be, for example, a dry film photoresist or a wetphotoresist.

As shown in FIG. 2B, in one embodiment an electroplating process formsthe first metal plating layer 262 on a portion of the top surface 202 aexposed by the first patterned mask 282. The first metal plating layer262 comprises a plurality of first lead metal patterns 262 a locatedoutside the chip bonding region 204, a plurality of bonding pad metalpatterns 262 b located outside the chip bonding region 204, a pluralityof second lead metal patterns 262 c located within the chip bondingregion 204, and a plurality of connecting segment metal patterns 262 dextending between the second lead metal patterns 262 c and the bondingpad metal patterns 262 b. Optionally, the first metal plating layer 262further comprises a first die pad pattern 262 e located within the chipbonding region 204, and the second metal plating layer 264 furthercomprises a second die pad pattern 264 e located within the chip bondingregion 204, for forming the aforementioned die pad 290 in FIGS. 1A and1B. Then, as shown in FIG. 2C, the first patterned mask 282 is removed.

Similarly, the method for forming the second metal plating layer 264comprises, forming a second patterned mask 284 on the undersurface 202 bof the conductive substrate 202. As shown in FIG. 2B, an electroplatingprocess is performed to form the second metal plating layer 264 on aportion of the undersurface 202 b exposed by the second patterned mask284. Then, as shown in FIG. 2C, the second patterned mask 284 isremoved.

As shown in FIGS. 2D-2F, using the first metal plating layer 262 as amask, a half etching process is performed on the conductive substrate202 to form recesses 208 in regions of the conductive substrate 202 notcovered by the first metal plating layer 262. When the half etchingprocess is performed, as shown in FIG. 2E, a photoresist layer 292 isformed on the undersurface 202 b of the conductive substrate 202 tocover and protect the second metal plating layer 264. After the halfetching process is performed, as shown in FIG. 2F, the photoresist layer292 is removed.

As shown in FIG. 2G, the filling material 240 is formed in the recesses208 in the chip bonding region 204 so that a flat region 240 a forplacing the chip 210 thereon can be provided. Example embodiments ofmethods for applying the filling material 240 comprise (i) applyingepoxy liquid onto the chip bonding region 204 by screen printing; or(ii) applying liquid photo-imageable solder mask ink on to the chipbonding region 204 by screen printing or spraying, exposing to thepattern and developing to remove the unnecessary portion; or (iii)attaching a dry film on the chip bonding region 204 by vacuumlaminating, and then exposing and developing. All three of the foregoingprocesses may be subject to a thermal cure of some type after thepattern is defined. Other embodiments of methods for applying thefilling material 240 are contemplated, and the foregoing examples shouldnot be treated as limiting.

As shown in FIG. 2H, the chip 210 is bonded to the chip bonding region204 of the conductive substrate 202 by an adhesion layer 270. The chip210 is located on the filling material 240 and the second lead metalpatterns 262 c. A wire bonding process is then performed so that thechip 210 is connected to the bonding pad metal patterns 262 b and to thefirst lead metal patterns 262 a through a plurality of bonding wires230. In alternative embodiments, when the filling material 240 is madeof a material having adhesive properties, such as the epoxy resin, thefilling material 240 itself can perform the functions of adhering andfixing the chip 210, allowing the adhesion layer 270 to be omitted.

With reference to FIG. 2I, a molding compound 250 is formed on the topsurface 202 a of the conductive substrate 202 to enclose the chip 210and the bonding wires 230, and the molding compound 250 fills up theremaining recesses 208. With reference to FIG. 2J, by using the secondmetal plating layer 264 as a mask, the undersurface of the conductivesubstrate 202 is etched to form a plurality of first leads 222 locatedoutside the chip bonding region 204, a plurality of bonding pads 226located outside the chip bonding region 204, a plurality of second leads224 located at least partially within the chip bonding region 204, and aplurality of connecting segments 228 connecting the second leads 224 andthe bonding pads 226. The die pad 290 can be formed by using theoptionally formed first die pad pattern 262 e and the optionally formedsecond die pad pattern 264 e as a mask. In the illustrated embodiment,and with reference to FIG. 1C, the filling material 240 encapsulates apart of each of the second leads 224 to provide a lead locking functionby mechanically adhering to the second leads 224. In certainembodiments, the filling material 240 may extend around the peaks 224 eof the second leads 224 to enhance the lead locking function, asdescribed above with respect to the encapsulant 250 and the first leads222.

Variations on the process illustrated in FIGS. 2A-2J are contemplated.For example, the die pad 290 may be omitted. Further, the second metalplating layer 264 shown in FIGS. 2B-2C may be formed on the undersurface202 b of the conductive substrate 202 after the molding compound 250shown in FIG. 2I is formed.

FIG. 2G′ illustrates an alternative variation on the process step shownin FIG. 2G. In this embodiment, a film material 241 having one or moreadhesive layers may be used in place of the filling material 240.Example film materials 241 include, without limitation, Nippon SteelChemical's NEX-130. In the illustrated embodiment, the film material 241is first attached on an undersurface of a wafer (not shown).Subsequently, the wafer is diced into a plurality of the chips 210 withthe film material 241 serving a similar function as the adhesive 211 andthe filling material 240. Then, similar to FIG. 2H, the chip 210 withthe film material 241 is bonded onto the chip bonding region 204. Thefilm material 241 is preferably sufficiently compliant to fill therecesses 208 and perform the lead locking function described above. Thefilm material 241 then may undergo a thermal cure process.

FIGS. 3A-3I are cross-sectional views illustrating a semiconductorpackaging process according to another of the present embodiments. Theembodiment of FIGS. 3A-3I is similar to the embodiment of FIGS. 2A-2J.However, in the embodiment of FIGS. 3A-3I omits the step of forming thefilling material 240, and the molding compound 250, in a later processstep, fills the recesses 208 including the recesses 208 under the chip210.

Referring to FIGS. 3A-3C, in one embodiment an electroplating processwith the use of the first patterned mask 282 forms the patterned firstmetal plating layer 262 on the top surface 202 a of the conductivesubstrate 202. The first metal plating layer 262 comprises a pluralityof first lead metal patterns 262 a located outside the chip bondingregion 204, a plurality of bonding pad metal patterns 262 b locatedoutside the chip bonding region 204, a plurality of second lead metalpatterns 262 c located within the chip bonding region 204, and aplurality of connecting segment metal patterns 262 d connecting thesecond lead metal patterns 262 c and the bonding pad metal patterns 262b. With the use of the second patterned mask 284, the patterned secondmetal plating layer 264 is formed on the undersurface 202 b of theconductive substrate 202 by, for example, an electroplating process.

As shown in FIGS. 3D-3F, by using the first metal plating layer 262 as amask, an etching process is performed on the conductive substrate 202 toform recesses 208 in the regions of the conductive substrate 202 notcovered by the first metal plating layer 262. In FIG. 3G, the chip 210is bonded to the chip bonding region 204 of the conductive substrate202. In the present embodiment the adhesion layer 270 is disposedbetween the undersurface of the chip 210 and the second leads 224 (thefilling material 240 and the die pad 290 are omitted in thisembodiment). The method for forming the adhesion layer 270 may compriseattaching an adhesive transfer tape on the undersurface of the chip 210and then bonding the chip 210 to the chip bonding region 204. The chip210 is then electrically connected to the first leads 222 and thebonding pads 226 through bonding wires 230.

With reference to FIG. 3H, a molding compound 250 is formed on the topsurface 202 a of the conductive substrate 202 to enclose the chip 210and the bonding wires 230. The molding compound 250 occupies at least aportion of the recesses 208, including the recesses 208 under the chip210. With reference to FIG. 3I, by using the second metal plating layer264 as a mask, the conductive substrate 202 is etched to form the firstleads 222 located outside the chip bonding region 204, the bonding pads226 located outside the chip bonding region 204, the second leads 224located at least partially within the chip bonding region 204, and theconnecting segments 228 connecting the second leads 224 and the bondingpads 226.

In an alternative embodiment (not shown), the second metal plating layer264 may be formed on the undersurface 202 b of the conductive substrate202 after the molding compound 250 (FIG. 3H) is formed.

FIGS. 4A-4J are cross-sectional views illustrating a semiconductorpackaging process according to another of the present embodiments. Theembodiment of FIGS. 4A-4J is similar to the embodiment of FIGS. 2A-2J.However, in the embodiment of FIGS. 4A-4J the photoresist layer acts asthe etching mask for forming the recesses 208. Further, the pattern ofthe first metal plating layer 262 formed in the embodiment of FIGS.4A-4J is different from that formed in the embodiment of FIGS. 2A-2J.Since the photoresist layer is used as an etching mask, only the firstlead metal patterns 262 a and the bonding pad metal patterns 262 b,which are used as the contacts, are formed in the embodiment of FIGS.4A-4J. Further, the second lead metal patterns 262 c and the connectingsegment metal patterns 262 d may be omitted. With reference to FIG. 4D,the top surface 202 a and the undersurface 202 b of the conductivesubstrate 202 can be covered by the same photoresist material 294 whilethe recesses 208 are formed. Therefore, the selection of the etchingsolution is relatively simple.

Referring to FIGS. 4A-4C, in one embodiment an electroplating processwith the use of the first patterned mask 282 forms the patterned firstmetal plating layer 262 on the top surface 202 a of the conductivesubstrate 202. The first metal plating layer 262 comprises a pluralityof first lead metal patterns 262 a outside the chip bonding region 204and a plurality of bonding pad metal patterns 262 b outside the chipbonding region 204. Moreover, with the use of the second patterned mask284, the patterned second metal plating layer 264 is formed on theundersurface 202 b of the conductive substrate 202 by, for example, anelectroplating process.

In FIG. 4D, a patterned photoresist layer 294 is formed on the topsurface 202 a of the conductive substrate 202 and a photoresist layer292 is formed on the undersurface 202 b of the conductive substrate 202.The photoresist layer 294 comprises a plurality of first leadphotoresist patterns 294 a located outside the chip bonding region 204,a plurality of bonding pad photoresist patterns 294 b located outsidethe chip bonding region 204, a plurality of second lead photoresistpatterns 294 c located at least partially within the chip bonding region204, and a plurality of connecting segment photoresist patterns 294 dconnecting the second lead photoresist patterns 294 c and the bondingpad photoresist patterns 294 b.

With reference to FIG. 4E, by using the photoresist layer 294 as a mask,a half etching process is performed on the upper surface 202 a of theconductive substrate 202 to form the recesses 208 in the regions of theconductive substrate 202 not covered by the photoresist layer 294.Thereafter, as shown in FIG. 4F, the photoresist layers 292 and 294 areremoved. With reference to FIG. 4G, the filling material 240 is formedin the recess 208 in the chip bonding region 204.

With reference to FIG. 4H, the chip 210 is bonded to the chip bondingregion 204 of the conductive substrate 202. The chip 210 is located onthe filling material 240. The chip 210 is then electrically connected tothe bonding pad metal patterns 262 b and the first lead metal patterns262 a through a plurality of bonding wires 230. With reference to FIG.4I, the molding compound 250 is formed on the top surface 202 a of theconductive substrate 202 to enclose the chip 210 and the bonding wires230, and the molding compound 250 at least partially fills the recesses208.

With reference to FIG. 4J, by using the second metal plating layer 264as a mask, the undersurface 202 b of the conductive substrate 202 isetched to form the first leads 222 located outside the chip bondingregion 204, the bonding pads 226 located outside the chip bonding region204, the second leads 224 located within the chip bonding region 204,and the connecting segments 228 connecting the second leads 224 and thebonding pads 226.

In an alternative embodiment (not shown), the second metal plating layer264 may be formed on the undersurface 202 b of the conductive substrate202 after the molding compound 250 (FIG. 4I) is formed.

FIGS. 5A-5I are cross-sectional views illustrating a semiconductorpackaging process according to another of the present embodiments. Theembodiment of FIGS. 5A-5I is similar to the embodiment of FIGS. 2A-2J.However, the embodiment of FIGS. 5A-5I omits the step of forming thefilling material 240, and the molding compound 250, in a later processstep, fills the recesses 208 including the recesses 208 under the chip210.

Referring to FIGS. 5A-5C, in one embodiment an electroplating processwith the use of the first patterned mask 282 forms the patterned firstmetal plating layer 262 on the top surface 202 a of the conductivesubstrate 202. The first metal plating layer 262 comprises a pluralityof first lead metal patterns 262 a outside the chip bonding region 204,and a plurality of bonding pad metal patterns 262 b outside the chipbonding region 204. Moreover, with the use of the second patterned mask284, the patterned second metal plating layer 264 is formed on theundersurface 202 b of the conductive substrate 202 by, for example, anelectroplating process.

In FIG. 5D, a patterned photoresist layer 294 is formed on the topsurface 202 a of the conductive substrate 202 and a photoresist layer292 is formed on the undersurface 202 b of the conductive substrate 202.The photoresist layer 294 comprises a plurality of first leadphotoresist patterns 294 a located outside the chip bonding region 204,a plurality of bonding pad photoresist patterns 294 b located outsidethe chip bonding region 204, a plurality of second lead photoresistpatterns 294 c located at least partially within the chip bonding region204, and a plurality of connecting segment photoresist patterns 294 dconnecting the second lead photoresist patterns 294 c and the bondingpad photoresist patterns 294 b.

With reference to FIG. 5E, by using the photoresist layer 294 as a mask,a half etching process is performed on the upper surface 202 a of theconductive substrate 202 to form the recesses 208 in a regions of theconductive substrate 202 not covered by the photoresist layer 294.Thereafter, as shown in FIG. 5F, the photoresist layers 292 and 294 areremoved. With reference to FIG. 5G, the chip 210 is bonded to the chipbonding region 204 of the conductive substrate 202. The chip 210 is thenelectrically connected to the bonding pad metal patterns 262 b and thefirst lead metal patterns 262 a through a plurality of bonding wires230. In the illustrated embodiment, the semiconductor package structurecomprises the adhesion layer 270 located between the undersurface of thechip 210 and the second leads 224.

With reference to FIG. 5H, a molding compound 250 is formed on the topsurface 202 a of the conductive substrate 202 to enclose the chip 210and the bonding wires 230, and the molding compound 250 at leastpartially fills the recesses 208, including the recesses 208 under thechip 210. With reference to FIG. 5I, by using the second metal platinglayer 264 as a mask, the conductive substrate 202 is etched to form thefirst leads 222 located outside the chip bonding region 204, the bondingpads 226 located outside the chip bonding region 204, the second leads224 located within the chip bonding region 204, and the connectingsegments 228 connecting the second leads 224 and the bonding pads 226.

In an alternative embodiment (not shown), the second metal plating layer264 may be formed on the undersurface 202 b of the conductive substrate202 after the molding compound 250 (FIG. 5H) is formed.

As illustrated by the foregoing description, the present embodimentsprovide several advantages. For example, the present embodiments enableleads located at least partially beneath the chip to be used for I/O.The present embodiments thus provide a semiconductor package that iscompact and has increased I/O density for greater performance in asmaller package. In certain embodiments an encapsulant and/or fillingmaterial surrounds peaks on the leads to increase the strength of themechanical hold on the leads, decreasing the likelihood that the leadswill separate from the package.

While the present invention has been described and illustrated withreference to specific embodiments thereof, these descriptions andillustrations do not limit the invention. It should be understood bythose skilled in the art that various changes may be made andequivalents may be substituted without departing from the true spiritand scope of the invention as defined by the appended claims. Theillustrations may not necessarily be drawn to scale. There may bedistinctions between the artistic renditions in the present disclosureand the actual apparatus due to manufacturing processes and tolerances.There may be other embodiments of the present invention which are notspecifically illustrated. The specification and the drawings are to beregarded as illustrative rather than restrictive. Modifications may bemade to adapt a particular situation, material, composition of matter,method, or process to the objective, spirit and scope of the invention.All such modifications are intended to be within the scope of the claimsappended hereto. While the methods disclosed herein have been describedwith reference to particular operations performed in a particular order,it will be understood that these operations may be combined,sub-divided, or re-ordered to form an equivalent method withoutdeparting from the teachings of the invention. Accordingly, unlessspecifically indicated herein, the order and grouping of the operationsare not limitations of the invention.

What is claimed is:
 1. A semiconductor package, comprising: asemiconductor chip; a plurality of first leads; a plurality of secondleads, each of the second leads being disposed at least partially underthe chip; a plurality of bonding pads extending outside a periphery ofthe chip; and a plurality of connecting segments connecting each bondingpad to a respective one of the second leads; wherein the connectingsegments include an angular offset routing between the second leads andthe bonding pads.
 2. The semiconductor package of claim 1, wherein uppersurfaces of the first leads, the second leads, the bonding pads, and theconnecting segments are coplanar.
 3. The semiconductor package of claim1, further comprising a first metal plating layer configured on theupper surface of each of the first leads, the upper surface of each ofthe second leads, the upper surface of each of the bonding pads, and theupper surface of each of the connecting segments, wherein the uppersurface of each of the first leads and the first metal plating layerabove the upper surface of each of the first leads are enclosed within apackage body, and the upper surface of each of the second leads and thefirst metal plating layer above the upper surface of each of the secondleads are enclosed within a filling material.
 4. The semiconductorpackage of claim 3, further comprising a second metal plating layerconfigured on the lower surface of each of the first leads and the lowersurface of each of the second leads, wherein the bonding pads and theconnecting segments are not covered by the second metal plating layer.5. The semiconductor package of claim 1, further comprising a fillingmaterial occupying spaces between the chip and the second leads.
 6. Thesemiconductor package of claim 5, further comprising a package body, andwherein a material of the filling material and a material of the packagebody are the same.
 7. A semiconductor package, comprising: asemiconductor chip; a plurality of first leads; a plurality of secondleads, each of the second leads being disposed at least partially underthe chip; a plurality of bonding pads extending outside a periphery ofthe chip; and a plurality of connecting segments connecting each bondingpad to a respective one of the second leads; wherein the connectingsegments include an angular offset routing between the second leads andthe bonding pads.
 8. The semiconductor package of claim 7, wherein anundersurface of the semiconductor chip is elevated above the uppersurfaces of the first leads and the bonding pads.
 9. The semiconductorpackage of claim 7, wherein the first leads have an upper sloped portionand a lower sloped portion meeting at a peak.
 10. The semiconductorpackage of claim 9, further comprising a package body that at leastpartially surrounds the peaks of the first leads to provide a mechanicalhold on the first leads.
 11. The semiconductor package of claim 7,further comprising a plurality of connecting segments connecting eachbonding pad to a respective one of the second leads, wherein uppersurfaces of the connecting segments are coplanar with the upper surfacesof the first leads, the second leads, and the bonding pads.
 12. Thesemiconductor package of claim 7, wherein upper surfaces of the secondleads do not include a metal plating layer.
 13. The semiconductorpackage of claim 7, further comprising a filling material occupyingspaces between the chip and the second leads.
 14. The semiconductorpackage of claim 13, further comprising a package body, and wherein amaterial of the filling material and a material of the package body arethe different.
 15. A semiconductor package, comprising: a semiconductorchip; a plurality of leads, a portion of the leads being disposed atleast partially under the chip; a plurality of bonding pads extendingoutside a periphery of the chip; a plurality of connecting segmentsconnecting each bonding pad to a respective one of the leads; and afilling material occupying spaces between the chip and the portion ofthe leads that are disposed at least partially under the chip; whereinthe connecting segments include an angular offset routing between theleads and the bonding pads.
 16. The semiconductor package of claim 15,further comprising a package body, and wherein a material of the fillingmaterial and a material of the package body are different.
 17. Thesemiconductor package of claim 15, wherein upper surfaces of the leads,the bonding pads and the connecting segments are coplanar.
 18. Asemiconductor packaging process, comprising: forming a patterned firstmetal plating layer on a top surface of a conductive substrate, whereinthe first metal plating layer comprises a plurality of first lead metalpatterns located outside of a chip bonding region of the substrate, aplurality of bonding pad metal patterns located outside of the chipbonding region, a plurality of second lead metal patterns located withinthe chip bonding region, and a plurality of connecting segment metalpatterns extending between the second lead metal patterns and thebonding pad metal patterns; performing a half etching process on the topsurface of the conductive substrate to form recessed areas in the topsurface, including recessed areas in the chip bonding region; bonding asemiconductor chip in the chip bonding region of the conductivesubstrate; wire bonding the semiconductor chip to the bonding pad metalpatterns and to the first lead metal patterns through a plurality ofbonding wires; and etching an undersurface of the conductive substrateto form a plurality of first leads located outside of the chip bondingregion, a plurality of bonding pads located outside of the chip bondingregion, a plurality of second leads located within the chip bondingregion, and a plurality of connecting segments extending between thesecond leads and the bonding pads, wherein the connecting segmentsinclude an angular offset routing between the second leads and thebonding pads.
 19. The semiconductor packaging process of claim 18,further comprising forming a patterned second metal plating layer on anundersurface of the conductive substrate.
 20. The semiconductorpackaging process of claim 18, further comprising inserting a fillingmaterial into the recessed areas in the chip bonding region.